The present invention relates to a semiconductor memory device.
Since a differential sense amplifier can, in general, operate stably and detect a small potential difference between input signals, it is frequently used in semiconductor memory devices. In a random-access memory (RAM), signals of two states which have an inverted relationship and represent the memory data read out from memory cells are supplied to a pair of input terminals of a differential sense amplifier through a pair of data lines. On the other hand, in a read-only memory (ROM), the memory data read out from memory cells are supplied through a single data line to a first input terminal of a differential sense amplifier which has a second input terminal connected to receive a reference potential signal from a dummy cell.
FIG. 1 shows a conventional mask ROM device formed of MOS transistors manufactured by the n-channel process. The ROM device includes a memory section 10, row and column decoders 12 and 14 coupled to the memory section 10, a differential sense amplifier 16, a data transmission circuit 18 which serves as a load circuit of the memory cells and which supplies the data read out from the memory section 10 to the first input terminal of the differential sense amplifier 16, a reference potential generator 20 for supplying a reference potential to the second input terminal of the differential sense amplifier 16, and an output buffer circuit 22 for generating an output signal corresponding to the output signal from the differential sense amplifier 16.
The memory section 10 includes, for example, a plurality of MOS transistors MC-11 to MC-MN which constitute memory cells respectively storing data "0" or "1" and which are arranged in a matrix form, and data line selection MOS transistors ST1 to STN, one end of each of which is connected to a corresponding one of digital lines DL1 to DLN of the matrix array of memory cells and the other ends of which are commonly connected.
The data transmission circuit 18 has a series circuit of resistors R1 and R2, which is connected between a power source terminal VC and ground; enhancement-type (E-type) MOS transistors TR1 and TR2, whose gates are connected to a connection point or node between the resistors R1 and R2, and one end of the current path of each of which is connected to the output terminal of the memory section 10; and a depletion-type (D-type) MOS transistor TR3, the gate and one end of the current path of which are connected to the other end of the current path of the MOS transistor TR2. The other end of the current path of each of the MOS transistors TR1 and TR3 is coupled to the power source terminal VC. The potential at the connection point between the MOS transistors TR2 and TR3 is transmitted to the first input terminal of the differential sense amplifier 16 as a data signal.
The reference potential generator 20 has resistors R3 and R4, E-type MOS transistors TR4 and TR5 and a D-type MOS transistor TR6, which have the same arrangement and connections as those of the resistors R1 and R2 and the MOS transistors TR1, TR2 and TR3. One end of the current path of each of the MOS transistors TR4 and TR5 is grounded through an MOS transistor TR7 of a similar arrangement as the MOS transistors ST1 to STN, and an MOS transistor TR8 of a similar arrangement as the MOS transistors MC-11 to MC-MN. A signal of logic level "1", that is, a voltage of a potential level equal to that at the gate of a selected data line selection MOS transistor, is supplied to the gate of the MOS transistor TR7. The gate of the MOS transistor TR8 receives an output voltage from a voltage divider formed of a series circuit of resistors R5 and R6 connected between the power source terminal VC and ground. The potential at the connection point between the MOS transistors TR5 and TR6 is supplied as the reference potential signal to the second input terminal of the sense amplifier 16.
In response to well known chip enable signals CE and CE, the sense amplifier 16 detects the difference between first and second input voltages V1 and V2, respectively applied to the first and second input terminals thereof, and supplies an output signal corresponding to this difference to the output buffer circuit 22.
The MOS transistors MC-11 to MC-MN of the memory section 10 have a high or low threshold voltage in accordance with the data to be stored. When an MOS transistor having, for example, a high threshold voltage is selected, it is kept OFF. Thus, the data line connected to this selected MOS transistor is charged, and the gradually increasing potential on this data line is supplied to the first input terminal of the sense amplifier 16. However, when an MOS transistor having a low threshold voltage is selected, this MOS transistor is turned on and the data line connected thereto is discharged. As shown in FIG. 2, in accordance with the stored data in the selected memory cell or the threshold voltage of the selected MOS transistor, a first input voltage V1 supplied to the first input terminal of the sense amplifier 16 gradually increases or decreases. Since a reference potential of substantially constant level is generated by the reference potential generator 20, a second input voltage V2 of a substantially constant level as shown in FIG. 2 is supplied to the second input terminal of the sense amplifier 16.
When the first input voltage V1, which increases or decreases in accordance with the charge/discharge operation of the data line, crosses the second input voltage V2, as shown in FIG. 2, the output signal from the sense amplifier 16 is inverted. An output signal V0 from the output buffer circuit 22 is also inverted as indicated by the broken line in FIG. 2. Thus, the readout speed of the memory data is largely dependent on the charge/discharge time. Therefore, various measures have been taken to shorten the charge/discharge time of the data line in an attempt to increase the readout speed of the memory data. However, improvements attainable with such measures are limited.